Added Master System Memory Bus
This commit is contained in:
@@ -9,9 +9,7 @@
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<ItemGroup>
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<Folder Include="Audio\" />
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<Folder Include="Cpu\" />
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<Folder Include="Interfaces\" />
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<Folder Include="Io\" />
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<Folder Include="Memory\" />
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</ItemGroup>
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</Project>
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8
Core/Interfaces/IAudioDevice.cs
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8
Core/Interfaces/IAudioDevice.cs
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@@ -0,0 +1,8 @@
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namespace Core.Interfaces
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{
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public interface IAudioDevice
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{
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// Now accepts the Beeper state + 3 AY frequencies + 3 AY volumes
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void AddSample(bool isHigh, float freqA, float volA, float freqB, float volB, float freqC, float volC);
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}
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}
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8
Core/Interfaces/IIoBus.cs
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8
Core/Interfaces/IIoBus.cs
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@@ -0,0 +1,8 @@
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namespace Core.Interfaces
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{
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public interface IIoBus
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{
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byte Read(ushort port);
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void Write(ushort port, byte value);
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}
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}
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9
Core/Interfaces/IMemory.cs
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9
Core/Interfaces/IMemory.cs
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@@ -0,0 +1,9 @@
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namespace Core.Interfaces
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{
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public interface IMemory
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{
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byte Read(ushort address);
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void Write(ushort address, byte value);
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void CleanRAMData();
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}
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}
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109
Core/Memory/SmsMemoryBus.cs
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109
Core/Memory/SmsMemoryBus.cs
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@@ -0,0 +1,109 @@
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using Core.Interfaces;
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using System;
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namespace Core.Memory
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{
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public class SmsMemoryBus : IMemory
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{
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// SMS has 8KB of internal Work RAM
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private readonly byte[] _workRam = new byte[0x2000];
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// The entire game cartridge loaded into one big array
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private byte[] _cartridgeRom = Array.Empty<byte>();
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// The Paging Registers (Which 16KB chunk is in which slot?)
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// Default startup state: Bank 0, 1, and 2 in order.
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private int _romBank0 = 0;
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private int _romBank1 = 1;
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private int _romBank2 = 2;
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// A flag to handle cartridges that don't use paging (like early 32KB games)
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private bool _isCartridgeLoaded = false;
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public void LoadCartridge(byte[] romData)
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{
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_cartridgeRom = romData;
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_isCartridgeLoaded = true;
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// Reset the mapper on boot
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_romBank0 = 0;
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_romBank1 = 1;
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_romBank2 = 2;
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// Clean the RAM
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CleanRAMData();
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}
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public byte Read(ushort address)
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{
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if (address < 0x4000) // ROM Slot 0 (0x0000 - 0x3FFF)
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{
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// SMS Hardware Quirk: The first 1KB (0x0000 - 0x03FF) is NEVER paged.
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// It is hardwired to Bank 0 so the interrupt handlers don't crash.
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if (address < 0x0400) return ReadFromCartridge(0, address);
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return ReadFromCartridge(_romBank0, address);
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}
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if (address < 0x8000) // ROM Slot 1 (0x4000 - 0x7FFF)
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{
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return ReadFromCartridge(_romBank1, address & 0x3FFF);
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}
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if (address < 0xC000) // ROM Slot 2 (0x8000 - 0xBFFF)
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{
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return ReadFromCartridge(_romBank2, address & 0x3FFF);
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}
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// If we are here, we are in System RAM (0xC000 - 0xFFFF)
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// The & 0x1FFF handles the 8KB mirroring automatically!
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return _workRam[address & 0x1FFF];
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}
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public void Write(ushort address, byte value)
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{
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if (address < 0xC000)
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{
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// You cannot write to a ROM cartridge!
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return;
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}
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// Write to System RAM
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_workRam[address & 0x1FFF] = value;
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// --- THE SEGA MAPPER ---
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// If the CPU wrote to the very top of memory, it is commanding a bank swap!
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if (address == 0xFFFD)
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{
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_romBank0 = value;
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}
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else if (address == 0xFFFE)
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{
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_romBank1 = value;
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}
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else if (address == 0xFFFF)
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{
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_romBank2 = value;
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}
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}
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private byte ReadFromCartridge(int bankIndex, int offset)
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{
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if (!_isCartridgeLoaded) return 0xFF; // Floating bus if no game
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int absoluteAddress = (bankIndex * 0x4000) + offset;
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// Safety check in case a game asks for a bank outside its file size
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if (absoluteAddress >= _cartridgeRom.Length)
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{
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// Wrap around (mirrors the ROM if it's smaller than the requested bank)
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absoluteAddress %= _cartridgeRom.Length;
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}
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return _cartridgeRom[absoluteAddress];
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}
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public void CleanRAMData()
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{
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Array.Clear(_workRam, 0, _workRam.Length);
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}
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}
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}
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