Add Z80 CPU skeleton, RegisterPair struct, and MemoryBus implementation

Core/Cpu/RegisterPair.cs

@@ -0,0 +1,17 @@
+using System.Runtime.InteropServices;
+
+namespace Core.Cpu
+{
+    [StructLayout(LayoutKind.Explicit)]
+    public struct RegisterPair
+    {
+        [FieldOffset(0)]
+        public ushort Word;
+
+        [FieldOffset(0)]
+        public byte Low;
+
+        [FieldOffset(1)]
+        public byte High;
+    }
+}

Core/Cpu/Z80.cs

@@ -0,0 +1,74 @@
+using System;
+using Core.Interfaces;
+
+namespace Core.Cpu
+{
+    public partial class Z80
+    {
+        // Main Register Set
+        public RegisterPair AF;
+        public RegisterPair BC;
+        public RegisterPair DE;
+        public RegisterPair HL;
+
+        // Alternate Register Set
+        public RegisterPair AF_Prime;
+        public RegisterPair BC_Prime;
+        public RegisterPair DE_Prime;
+        public RegisterPair HL_Prime;
+
+        // Index Registers
+        public RegisterPair IX;
+        public RegisterPair IY;
+
+        // Special Purpose Registers
+        public ushort PC; // Program Counter
+        public ushort SP; // Stack Pointer
+        public byte I;    // Interrupt Vector
+        public byte R;    // Memory Refresh
+
+        // The Memory Bus
+        private readonly IMemory _memory;
+
+        public Z80(IMemory memory)
+        {
+            _memory = memory;
+            Reset();
+        }
+
+        public void Reset()
+        {
+            PC = 0x0000;
+            // The Z80 initializes SP to 0xFFFF on boot
+            SP = 0xFFFF;
+
+            AF.Word = 0;
+            BC.Word = 0;
+            DE.Word = 0;
+            HL.Word = 0;
+        }
+
+        public int Step()
+        {
+            // Fetch the next opcode and increment the Program Counter
+            byte opcode = _memory.Read(PC++);
+
+            // Decode and execute
+            return ExecuteOpcode(opcode);
+        }
+
+        private int ExecuteOpcode(byte opcode)
+        {
+            switch (opcode)
+            {
+                case 0x00: // NOP (No Operation)
+                    return 4; // Takes 4 T-states
+
+                // We will expand this massive list soon!
+
+                default:
+                    throw new NotImplementedException($"Opcode 0x{opcode:X2} at PC 0x{(PC - 1):X4} is not implemented.");
+            }
+        }
+    }
+}