Got main system and VDP working! There is a display!

This commit is contained in:
2026-05-10 02:43:11 +01:00
parent 778f03b55c
commit f4e279b9c8
8 changed files with 516 additions and 104 deletions

View File

@@ -1275,6 +1275,18 @@ namespace Core.Cpu
switch (extendedOpcode)
{
case 0x41: // OUT (C), B
_simpleIoBus.WritePort(BC.Word, BC.High);
return 12;
case 0x49: // OUT (C), C
_simpleIoBus.WritePort(BC.Word, BC.Low);
return 12;
case 0x61: // OUT (C), H
_simpleIoBus.WritePort(BC.Word, HL.High);
return 12;
case 0x69: // OUT (C), L
_simpleIoBus.WritePort(BC.Word, HL.Low);
return 12;
case 0x43: // LD (nn), BC
ushort dest43 = FetchWord();
WriteMemory(dest43, BC.Low);
@@ -1494,6 +1506,48 @@ namespace Core.Cpu
if ((n & 0x02) != 0) AF.Low |= 0x20; // Bit 5 from bit 1
return 16;
}
case 0xA3: // OUTI
{
// 1. Read data from memory at HL
byte valA3 = ReadMemory(HL.Word);
// 2. Decrement the B register
BC.High--;
// 3. Output the data to the port specified by C
_simpleIoBus.WritePort(BC.Word, valA3);
// 4. Increment the memory pointer
HL.Word++;
// 5. Update Flags (N is always set. Z is set if B reached 0)
AF.Low |= 0x02;
if (BC.High == 0) AF.Low |= 0x40;
else AF.Low &= 0xBF;
return 16;
}
case 0xB3: // OTIR
{
// This does exactly the same thing as OUTI, but loops until B == 0
byte valB3 = ReadMemory(HL.Word);
BC.High--;
_simpleIoBus.WritePort(BC.Word, valB3);
HL.Word++;
AF.Low |= 0x02;
if (BC.High != 0)
{
AF.Low &= 0xBF; // Z is reset
PC -= 2; // Loop back and execute ED B3 again!
return 21;
}
else
{
AF.Low |= 0x40; // Z is set
return 16;
}
}
case 0xB0: // LDIR
{
byte val00 = ReadMemory(HL.Word);